Generally, signal synchronizing and frequency synthesis circuitry (SSFSC), such as Phase Lock Loops (PLLs) and Delay Lock Loops (DLLs), are used in maintaining the synchronous operation of microprocessor systems. In integrated circuit (IC) logic, signal synchronizing and synthesis circuitry, such as PLLs and DLLs, are utilized in order to minimize timing delays or errors. Accordingly, such signal synchronizing and synthesis circuitry allows for the synchronization of multiple signals to conform to a desired target frequency signal. The synchronization of multiple operating signals allows multiple circuits within a system to operate in accordance with a desired timing protocol. In such applications as computer systems, the various components of the microprocessor system require synchronous operation in order to perform in accordance with a desired operating protocol standard.
Generally, synchronizing or timing problems occur when various clock signals operating within the system lose phase alignment or become skewed while passing through intermediate circuitry having variant propagation delays. In a high-speed multiple chip computer system, it is particularly important to maintain the phase difference between clock signals at different sections of the system to a specified minimum value. Nevertheless, variations in propagation can be caused by circuitry structure variables or tolerance variables associated with the manufacturing process. Another synchronizing or timing problem may occur with respect to typical microprocessor systems that have an external clock signal (XCLK) and another internal clock signal (CLKIN) which is internal to the microprocessor core. These two clock signals may sometimes become skewed (out of phase) with relation to each other, as between the clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core.
Typically, the synchronous operation of a microprocessor system, along with the various logic components and sub-systems therein, is accomplished through the use of one or more clock signals. Each component within the system utilizes a clock signal for synchronizing the operation of its own internal sequential logic circuitry to that of the system in order to provide operation in accordance with the desired operating protocol standard. Therefore, in high-speed systems, the synchronous operation of clock signals with respect to each of the clocked components must be maintained with high efficiency or else multiple system timing errors and delays can result. Two well-known systems utilized in maintaining the synchronous operation of microprocessor systems are the phase lock loop (PLL) and the delay lock loop (DLL).
The DLL is a type of feedback control system that attempts to maintain a constant or zero phase difference between the clock signals at different sections within the system. The conventional DLL 100, as shown in FIG. 1A, is comprised of a phase detector 102, a counter 104, a multiplexer 106, and a delay line element 108, which are interconnected to form a feedback DLL system. The DLL 100, in operation, receives a reference signal (REFCLK) at both the phase detector 102 and the delay line element 108. The delay line element 108 generates duplicate signals of the reference signal (REFCLK-N) called taps 110, each of the taps 110 are delayed by a selected time period and output to the multiplexer 106. The counter 104 receives the output from the phase detector 102 and selects which tap output 110 from the delay line element 108 will be propagated to the multiplexer output (CLKOUT). The multiplexer output (CLKOUT) is then looped back via a feedback line to the phase detector 102, wherein the phase detector 102 generates a phase error value which is supplied to the counter 104. Based upon the phase error value, the counter 104 generates a signal to correct the phase error, counting upwards when the (CLKOUT) leads (REFCLK), or counting downwards when the (CLKOUT) lags (REFCLK). Based on the counter value, the timing of the multiplexer output is either advanced or delayed until the (CLKOUT) signal is in phase or coincident with the phase of the (REFCLK) signal.
Likewise, the PLL is a type of feedback control system that attempts to maintain a constant or zero phase difference between the two signals (REFCLK and FB) in order to prevent timing errors which can lead to delays in microprocessor operation. The conventional PLL 120, as shown in Figure 1B, includes a phase detector 122, charge pump 124, loop filter 126, a voltage controlled oscillator (VCO) 128, a clock distribution tree 130, and a frequency divider device 132 which are interconnected to form a feedback PLL system.
In operation, the phase detector 122 receives an input signal (REFCLK) and a feedback signal (FB), the feedback signal (FB) being the CLKOUT signal from the VCO 128 which has been passed through the clock distribution tree 130 and the divider device 132. The phase detector 122 compares the input signal (REF) and the feedback signal (FB) in order to determine if there is any phase difference between the two signals. If a phase difference is detected, the phase detector 122 generates either an UP or DN signal in order to pump a control voltage (VCNTL) higher or lower. For example, if the REFCLK signal leads the FB signal, then the phase detector 122 would activate the UP signal a specific amount corresponding to the phase difference. Alternately, if the FB signal leads the REFCLK signal, then the phase detector 122 would activate the DN signal a specific amount corresponding to the phase difference. If the input signal (REFCLK) and the feedback signal (FB) are locked or in-phase, then neither the UP or DN signals are activated.
The charge pump 124 then converts the digital state (UP/DN) of the phase detector 122 into an analog control voltage (VCNTL) which is used to operate and control the voltage controlled oscillator (VCO) 128. The control voltage signal (VCNTL) is then applied to the VCO 128 which varies the set frequency of the VCO 128 in a direction which reduces the frequency difference or phase error between the input signal (REF) and the feedback signal (FB). The signal is then supplied to the clock distribution tree 130 and then to the frequency divider device 132, before being applied back to the phase detector 122. The process is repeated until the REF and FB signals become synchronized and the lock state is achieved.
Generally, a typical microprocessor requires a PLL, a DLL, or both in order to address the various synchronization and frequency synthesis problems that arise in connection with typical microprocessor operations. Accordingly, a question arises on whether to use a PLL or a DLL for frequency synthesis and synchronization. The stability and jitter of a PLL, as compared to a DLL, where it can be used for frequency synthesis, has typically maintained a better jitter performance since the jitter accumulated by the end of the line does not contribute to the next clock cycles.
The conventional or currently available PLL and the DLL circuits, however, each require their own respective circuitry to perform their respective operative tasks. Accordingly, the requirement of having two separate and unique circuits (PLL and DLL) to address the different synchronization and frequency synthesis problems which arise with respect to typical microprocessor operations, necessarily increases the amount of space needed to support these circuits. Moreover, the requirement of the two separate circuits also increases the complexity of the system as different signals need to be switched and routed to different circuitry depending on the timing problems encountered. Additionally, having two separate and unique circuits (PLL and DLL) to address the different synchronization problems necessarily increases the overall cost of the microprocessor system.
It is therefore desirable to provide a single circuit that provides the configurable operation of both a PLL and a DLL to a microprocessor without utilizing the amount of space which is typically used in separate PLLs and DLLs. Moreover, it would be desirable to provide a single circuit that provides the operation of both the PLL and the DLL without increasing the complexity and cost of the system.